The present invention relates to an electrode structure of an integrated circuit and method for forming the package therefor. The invention also relates to electronic circuitry mounting schemes for forming circuit networks by mounting a semiconductor IC chip on a carrier substrate and providing electrical interconnections therefor, and more particularly to the electrode structure of semiconductor ICs and its packaging formation method adaptable for use in attaining a low cost mount with increased integration density.
Conventionally, most semiconductor devices having an IC chip employ chip-mount methodology which makes use of wire-bonding or tape-automated bonding technology for electrical interconnections of carrier substrates known as "lead frames."
These carrier substrate are typically molded using certain plastic material after completion of the necessary electrical connections. Overhang portions of leads are wire-bonded by soldering to several or all of the solder pads provided on an associated circuit board.
In the recent years, as a further reduction in size or "down-sizing" is more strictly demanded for electronic modules, it is becoming important more and more to decrease or "miniaturize" the mount area that semiconductor IC packages occupy on the circuit board.
One currently available approach to attain this is to develop a bare-chip mount scheme and chip-size packaging. On the other hand, where an increased number of bonding pads are provided on a chip of limited surface area, what is called the "flip-chip(FC)" interconnection scheme may be desirable.
This scheme is to employ an area-electrode structure which has a grid array of bonding pads spanning substantially the entire surface of an IC chip, for achievement of electrical interconnections by use of solder bumps. This may offer the capability of allowing the pads to increase in distance between adjacent ones thereof and the ability to minimize the inductance at pad connections.
Unfortunately, prior known semiconductor IC devices with the above packaging schemes do not come without an accompanying problem: forming of FC connections serves to increase the risk of occurrence of a failure due to unwanted electrical short-circuiting between adjacent solder bumps during solder-reflow process. This is due to the fact that since most IC chips are inherently designed under an assumption that their bonding pads assume use of wire bonding techniques, layout of such pads must be "crowded" on the periphery of an IC chip causing the pad distance or pitch to decrease accordingly. Providing FC connections for such short-distance spanning bonding pads results in an increase in possibility of shortcircuiting to occur between adjacent pads.
Another problem encountered with the prior art is that where the TAB or FC schemes are employed for electrical interconnection of an IC chip, a special metalization process should be required to enhance or maximize the reliability of bonding pads concerned. This in turn leads to a decrease in commercial availability of such special type of IC chips as well as an increase in production costs.
In most cases the IC chip's bonding pads for external connection are made of aluminum, which remains relatively inferior in solderability; even when wetness is attained to some extent, aluminum tends to rapidly diffuse into a soldering material causing applicability for soldering to decrease. To ease or avoid such difficulty, the bonding pads for FC connection are typically comprised of a multi-layered structure such as a hybrid of chromium (Cr), copper (Cu) and gold (Au) films being sequentially laminated on an aluminum base electrode.
In view of the foregoing, it is rather difficult to obtain IC chips having FC electrode pads adaptable for use in high-density mount packaging. Even where such IC chips are available, a limitation in type must exist while prices are high, lowering applicability. This is a further problem faced with the prior art semiconductor IC packaging.
One possible approach to avoid the above problems is the use of ball grid array (BGA) packages, one of which has been described in, for example, U.S. Pat. No. 5,216,278 issued Jun. 1, 1993 to Lin et al. and assigned to Motorola, Inc. With the BGA package disclosed, an IC chip having bonding pads is mounted to a carrier substrate while letting the pads be wire-bonded for electrical interconnection to bonding areas in package leads on the substrate. These bonding areas in turn are connected by conductive through-holes called the "filled vias" to a grid array of terminal solder pads on the bottom surface of the carrier substrate. The solder pads act as FC connection electrodes which permits connection of the IC chip with external circuitry outside of the substrate. With such BGA packaging scheme, the IC chip with wire-bonding pads is capable of being electrically coupled at the FC pads to any desired external circuits.
Unfortunately, this prior art suffers from a problem in that the carrier substrate for pad layout conversion becomes larger in size than an IC chip being mounted thereto. This is true because the IC chip is electrically coupled to FC pads by use of wire leads. More specifically, wires are employed as electrical connections for the IC pads, which wires extend outwardly from the pads to be bonded with corresponding soldering areas of package leads on the top surface of the carrier substrate, which in turn are coupled to the FC pads on the substrate bottom surface by way of conductive via holes--say, "vias"--that are formed in the substrate at locations outside the soldering areas.
Another disadvantage of the prior art is that the BGA packaging as taught by U.S. Pat. No. 5,216,278 will be difficult to satisfy strict requirements regarding accomplishment of high-frequency characteristics of semiconductor IC devices. In the prior art, since no consideration is given as to how the pad layout conversion carrier substrate is arranged in structure, the package leads will possibly include those being increased in length causing inductance thereat to increase accordingly.
Still another disadvantage is that where the soldering pads are further increased in number in the near future, it will possibly be happen that all of such pads can no longer be successfully wire-bonded for electrical connection due to the insufficiency of wiring density in double-surface wiring substrates. If this were the case, multiple layer structure will be required for the carrier substrate. However, use of such multilayer structure can result in an increase in production cost while increasing complexity. In light of the above, it can hardly be said that the prior art BGA packaging is suitable for high pin count applications.